1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device performing overheat protection efficiently.
2. Description of the Related Art
Recently, a variety of different types of high performance-electrical equipment, such as computer systems and mobile phones, have developed rapidly and come to be used widely. Such electrical equipment requires a high performance power circuit, and such a power circuit is generally integrated into a semiconductor device. The power circuit includes a constant-voltage-generation circuit to achieve a stable operation.
Such a semiconductor device having a constant-voltage-generation circuit commonly employs a protection circuit to avoid destruction due to a latch-up phenomenon triggered by an accidental surge pulse. An over-current protection circuit is generally used as the protection circuit for the constant-voltage-generation circuit. However, if a voltage difference between input and output voltages is large, a temperature of the semiconductor chip increases rapidly especially around an output transistor and may exceed a maximum rating before the over-current protection circuit is effective.
A variety of power protection methods are used to avoid such an overheat condition. In one example of such power protection methods, a product of an input voltage and an output current is checked and used to protect the semiconductor device. In this power protection method, however, it is necessary to detect both voltage and current. Accordingly, a complicated multiplication circuit is required. As a result, the size of the semiconductor device increases due to employment of the complicated multiplication circuit.
Because of the drawback described above, an overheat protection circuit that protects the semiconductor device based on the temperature of the semiconductor device may be used instead of using the power protection method. Such an overheat protection circuit generally employs a thermal-shut-down circuit.
FIG. 1 illustrates a background thermal-shut-down circuit 10. The thermal-shut-down circuit 10 includes an output terminal 101, a constant current source 102, a diode 103, a comparator 104, an operational amplifier 105, an NMOS (N-type Metal Oxide Semiconductor) transistor 106, resistors 107 through 109, a reference voltage generator 110, and a capacitor 114. In the thermal-shut-down circuit 10, a bias current is supplied to the diode 103 from the constant current source 102. The diode 103 detects the temperature of the semiconductor chip under the bias current. The comparator 104 compares a voltage VF at an anode of the diode 103 with a reference voltage Vr generated by the operational amplifier 105, the reference voltage generator 110, the resistors 107 through 109, and the capacitor 114. When the temperature of the semiconductor device increases and an anode voltage of the diode 103 VF drops below the reference voltage Vr, an output signal of the comparator 104 is inverted so as to output an overheat protection signal to the output terminal 101.
FIG. 2 illustrates a constant voltage circuit 1 that includes the thermal-shut-down circuit 10 of FIG. 1.
In FIG. 2, the reference voltage Vr in FIG. 1 is indicated by Vr2. Similarly, the constant current source 102, the diode 103 VF, and the comparator 104 are indicated by I1, D1, and 11a respectively. An output of the thermal-shut-down circuit 10 is wired to a gate of an output transistor M1. When the temperature of the semiconductor chip increases and the anode voltage VF of the diode D1 decreases below the reference voltage Vr2, an output voltage of the comparator 11a becomes high, making a gate voltage of the output transistor M1 high to shut off the output transistor M1. As a result, the semiconductor chip can be prevented from overheating.
In FIG. 2, the highest temperature portion in the semiconductor chip is located around the output transistor M1. Therefore, the diode D1 that is the temperature detector may be disposed as close to the output transistor M1 as possible.
FIG. 3 illustrates a cross-sectional schematic view of a semiconductor device that includes the output transistor M1 and the diode D1. In FIG. 3, the output transistor M1 is provided on the left side and the diode D1 is provided on the right side, respectively. A P-type substrate (Psub) 21 is employed in this semiconductor device. As for the output transistor M1, an N− region 18 is formed on the P-type substrate 21. Further, two P+ regions 11 and 12 are formed in the N− region 18. The P+ region 11 is a drain electrode D of the output transistor M1 and the P+ region 12 is a source electrode S. A gate electrode is formed between the P+ regions 11 and 12.
An N+ region 13 is formed in the N− region 18 and is connected to power supply Vdd. The source electrode S of the output transistor M1 is connected to power supply Vdd and the drain electrode D is connected to the output terminal Vout of the constant voltage circuit 1 by wiring provided on the semiconductor chip.
The diode D1 is formed by a short circuit of a base and a collector of an NPN transistor. The NPN transistor is formed in an Nwell 20 formed in the P-type substrate 21. An N+ region 15 and a P− region 19 are formed in the Nwell 20. Further, a P+ region 16 and an N+ region 17 are formed in the P− region 19. The N+ region 15 is a collector of the NPN transistor. Similarly, P+ region 16 is a base of the NPN transistor, and the N+ region 17 is an emitter of the NPN transistor, respectively. The N+ region 15 that is the collector of the NPN transistor, and the P+ region 16 that is the base of the NPN transistor are connected to form the diode D1. A connection node of the N+ regions 15 and the P+ region 16 is an anode A of the diode D1. The N+ region 17 that is the emitter of the NPN transistor is a cathode K of the diode D1. The cathode K of the diode D1 is connected to a P+ region 14 formed in the P-type substrate 21 by wiring. The P+ region 14 is connected to ground Vss.
When devices are formed on the P-type substrate 21, it is known that some parasitic elements are formed unintentionally on the semiconductor device. In FIG. 3, for example, PNP transistors Q1 and Q2, and a NPN transistor Q3 are formed unintentionally. The PNP transistor Q1 includes an emitter that is the P+ region 11, a base that is the N− region 18, and a collector that is the P-type substrate 21. The PNP transistor Q2 includes an emitter that is the P+ region 12, a base that is the N− region 18, and a collector that is the P-type substrate 21. The NPN transistor Q3 includes a collector that is the N− region 18, and a base that is the P-type substrate 21, and an emitter that is the Nwell region 20.
FIG. 4 illustrates a circuit diagram showing these three parasitic transistors Q1, Q2 and Q3, the diode D1, and the constant current source I1. In FIG. 4, an area surrounded by a dotted line represents a circuit block comprising parasitic transistors. Resistors R11 and R12 are resistances at each region. As shown in FIG. 4, the emitter of the PNP transistor Q1 is connected to the output terminal Vout, the collector is connected to the collector of the PNP transistor Q2 and to the base of the NPN transistor Q3. Further, the base of the PNP transistor Q1 is commonly connected to the base of the PNP transistor Q2.
The source of the PNP transistor Q2 is connected to the power supply terminal Vdd. The resistor R11 is connected between the source and the base of the PNP transistor Q2. The base of the PNP transistor Q2 is connected to the collector of the NPN transistor Q3. The emitter of the NPN transistor Q3 is connected to the anode A of the diode D1 and the base of the NPN transistor Q3 is connected to ground through the resistor R12.
When a high surge voltage is applied to the output terminal Vout, a voltage at the emitter of the PNP transistor Q1 rises. When the voltage at the emitter of the PNP transistor Q1 exceeds 0.7 v above a voltage at the power supply terminal Vdd, a base current flows at the PNP transistor Q1. Consequently, the PNP transistor Q1 turns on. Since a surge current flows through the resistor R12, the NPN transistor Q3 turns on due to a voltage drop at the resistor R12. Further, the PNP transistor Q2 turns on due to a voltage drop generated at the resistor R11.
Once the PNP transistor Q2 is on, the voltage drop at the resistor R12 is kept due to a collector current of the PNP transistor Q2 even after the surge voltage is stopped. Consequently, the NPN transistor Q3 is kept on. As a result, current keeps flowing from the power supply terminal Vdd to ground Vss through two paths, i.e., a path through the PNP transistor Q2 and the resistor R12, and a path through the resistor R11 and the NPN transistor Q3. This phenomenon is known as “latch-up phenomenon” (or simply “latch-up”)
When the diode D1 is placed closer to the output transistor M1 for detecting the temperature of the output transistor M1 quickly and accurately, a latch-up current increases because the collector current of the PNP transistor Q2 and NPN transistor Q3 increase. Accordingly, wiring formed on the semiconductor chip may be melted and the circuit destroyed.